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*****
UPD65016GB-041-3B4 (1/2) IL16
C-MOS MULTI FUNCTION GATE
-TOP VIEW- 33 32 31 30 29 28 27 26 25 24 23 34 35 36 37 38 39 40 41 42 43 44 GND
VDD
GND
22 21 20 19 18 17 16 15 14 13 12
1 2 3 4 5 6 7 8 9 10 11
(VDD = +5V) PIN NO. 23 24 25 26 27 28 29 30 31 32 33 I/O I I I I I I I I O I SIGNAL A7 A6 A5 A4 A3 A2 A1 A0 GND HCLK OE PIN NO. 34 35 36 37 38 39 40 41 42 43 44 I/O O O O O O O O O I I SIGNAL D7 D6 D5 D4 D3 VDD D2 D1 D0 C7 C6
PIN NO. 1 2 3 4 5 6 7 8 9 10 11
I/O I I I I I I I I I I I
SIGNAL C5 C4 C3 C2 C1 C0 B7 B6 B5 B4 B3
PIN NO. 12 13 14 15 16 17 18 19 20 21 22
I/O I I I I I I I I I I
SIGNAL B2 B1 B0 MD1 MD0 GND CLK F3 F2 F1 F0
UPD65016GB-041-3B4 (2/2)
23 24 25 26 27 28 29 30 34 35 36 37 38 40 41 42
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
MODE MD1 MD0 L L VARIABLE LENGTH SHIFT REGISTER L H SORTING REGISTER L TIMING GENERATOR H H 3 to 1 MULTIPLEXER WITH D-FF H LOW LEVEL : GND HIGH LEVEL: +5V MODE-0 INPUT A0-A7 F0-F3 MODE-1 INPUT A0-A7 B0-B7 F0 F1 F2 F3 MODE-2 INPUT A0-A7 F0 F1 OUTPUT HCLK MODE-3 INPUT A0-A7 B0-B7 C0-C7 F0, F1 F2 F3
***** MODE-0 ***** MODE-1 ***** MODE-2 ***** MODE-3
7 8 9 10 11 12 13 14
B7 B6 B5 B4 B3 B2 B1 B0
: SHIFT REGISTER : DELAY CONTROL
43 44 1 2 3 4 5 6
C7 C6 C5 C4 C3 C2 C1 C0
: LOWER 8 BITS : UPPER 8 BITS : SYNC : GRAPH/MOTION SELECT : INVERT 2SB-LSB (D6-D0) WHEN H : INVERT MSB (D7) WHEN H
: INTERVAL ROM DATA : COUNTER ENABLE : LOAD
19 20 21 22
F3 F2 F1 F0 32
: HALF CLOCK OUTPUT
18 15 16 33
CLK MD1 MD0 OE
HCLK
: GROUP A : GROUP B : GROUP C : SELECT FOR GROUP A TO C : INVERT 2SB to LSB (D6 to D0) WHEN H : INVERT MSB (D7) WHEN H
ALL MODE INPUT CLK : SYSTEM CLOCK MD0,MD1 : MODE CONTROL OE : OUTPUT ENABLE OUTPUT D0-D7
: DATA

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